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Zorro II

86 PIN EDGE CONNECTOR (at the A2000)

86 PIN EDGE CONNECTOR at the A2000.

Pin A500 A1000 A2000 A2000B Name Description
1 X X X X GND Ground
2 X X X X GND Ground
3 X X X X GND Ground
4 X X X X GND Ground
5 X X X X +5V +5 Volts DC
6 X X X X +5V +5 Volts DC
7 X X X X n/c  
8 X X X X -5V -5 Volts DC
9 X X     n/c  
      X X 28CLOCK 28MHz Clock
10 X X X X +12V +12 Volts DC
11 X X     n/c  
      X X /COPCFG Configuration Out
12 X X X X CONFIG IN, Grounded  
13 X X X X GND Ground
14 X X X X /C3 C3 Clock
15 X X X X CDAC Clock
16 X X X X /C1 C1 Clock
17 X X X X /OVR  
18 X X X X RDY Ready
19 X X X X /INT2 Interrupt 2
20 X X     /PALOPE  
      X   n/c  
        X /BOSS  
21 X X X X A5 Address 5
22 X X X X /INT6 Interrupt 6
23 X X X X A6 Address 6
24 X X X X A4 Address 4
25 X X X X GND Ground
26 X X X X A3 Address 3
27 X X X X A2 Address 2
28 X X X X A7 Address 7
29 X X X X A1 Address 1
30 X X X X A8 Address 8
31 X X X X FC0 Processor status 0
32 X X X X A9 Address 9
33 X X X X FC1 Processor status 1
34 X X X X A10 Address 10
35 X X X X FC2 Processor status 2
36 X X X X A11 Address 11
37 X X X X GND Ground
38 X X X X A12 Address 12
39 X X X X A13 Address 13
40 X X X X /IPL0  
41 X X X X A14 Address 14
42 X X X X /IPL1  
43 X X X X A15 Address 15
44 X X X X /IPL2  
45 X X X X A16 Address 16
46 X X X X /BEER Bus Error
47 X X X X A17 Address
48 X X X X /VPA  
49 X X X X GND Ground
50 X X X X ECLK E Clock
51 X X X X /VMA  
52 X X X X A18 Address 18
53 X X X X RST Reset
54 X X X X A19 Address 19
55 X X X X /HLT Halt
56 X X X X A20 Address 20
57 X X X X A22 Address 22
58 X X X X A21 Address 21
59 X X X X A23 Address 23
60 X X     /BR  
      X X /CBR  
61 X X X X GND Ground
62 X X X X /BGACK  
63 X X X X D15 Data 15
64 X X     /BG  
      X X /CBG  
65 X X X X D14 Data 14
66 X X X X /DTACK  
67 X X X X D13 Data 13
68 X X X X R/W Read/Write
69 X X X X D12 Data 12
70 X X X X /LDS  
71 X X X X D11 Data 11
72 X X X X /UDS  
73 X X X X GND Ground
74 X X X X /AS  
75 X X X X D0 Data 0
76 X X X X D10 Data 10
77 X X X X D1 Data 1
78 X X X X D9 Data 9
79 X X X X D2 Data 2
80 X X X X D8 Data 8
81 X X X X D3 Data 3
82 X X X X D7 Data 7
83 X X X X D4 Data 4
84 X X X X D6 Data 6
85 X X X X GND Ground
86 X X X X D5 Data 5
Contributor: Joakim Ögren
Source: ?

Copyright © The Hardware Book Team 1996-2004.
May be copied and redistributed, partially or in whole, as appropriate.
Document last modified: 2002-01-10