(at the computer)
80 PIN ??? CONNECTOR at the computer.
Pin | Name | Description |
---|---|---|
1 | GND | Ground |
2 | GND | Ground |
3 | VCC | +5 VDC |
4 | VCC | +5 VDC |
5 | /CFGOUT | Configout AutoConfig signal (not connected) |
6 | /CFGIN | Configin AutoConfig signal (grounded) |
7 | GND | Ground |
8 | CCKQ | 3.58 MHz CCKQ clock (C3) |
9 | CDAC | 7.16 MHz CDAC clock (90° before system clock) |
10 | CCK | 3.58 MHz CCK clock (C1) |
11 | /OVR | Override (Disables /DTACK generation of Gary) |
12 | XRDY | External Ready (Generates wait states while low). |
13 | /INT2 | Level 2 Interrupt |
14 | n/c | not connected |
15 | A5 | Address Bus 5 |
16 | /INT6 | Level 6 Interrupt |
17 | A6 | Address Bus 6 |
18 | A4 | Address Bus 4 |
19 | GND | Ground |
20 | A3 | Address Bus 3 |
21 | A2 | Address Bus 2 |
22 | A7 | Address Bus 7 |
23 | A1 | Address Bus 1 |
24 | A8 | Address Bus 8 |
25 | /FC0 | Processor Function Code Status (bit 0) |
26 | A9 | Address Bus 9 |
27 | /FC1 | Processor Function Code Status (bit 1) |
28 | A10 | Address Bus 10 |
29 | /FC2 | Processor Function Code Status (bit 2) |
30 | A11 | Address Bus 11 |
31 | GND | Ground |
32 | A12 | Address Bus 12 |
33 | A13 | Address Bus 13 |
34 | /IPL0 | Interrupt Priority Level (bit 0) |
35 | A14 | Address Bus 14 |
36 | /IPL1 | Interrupt Priority Level (bit 1) |
37 | A15 | Address Bus 15 |
38 | /IPL2 | Interrupt Priority Level (bit 2) |
39 | A16 | Address Bus 16 |
40 | /BERR | Bus Error |
41 | A17 | Address Bus 17 |
42 | /VPA | Valid Peripheral Address (asserted by Gary) |
43 | GND | Ground |
44 | E | E Clock |
45 | /VMA | Valid Memory Address (asserted by Gary) |
46 | A18 | Address Bus 18 |
47 | /RST | Reset |
48 | A19 | Address Bus 19 |
49 | /HLT | Halt |
50 | A20 | Address Bus 20 |
51 | A22 | Address Bus 22 |
52 | A21 | Address Bus 21 |
53 | A23 | Address Bus 23 |
54 | /BR | Bus Request |
55 | GND | Ground |
56 | /BGACK | Bus Grant Acknowledge |
57 | D15 | Data Bus 15 |
58 | /BG | Bus Grant |
59 | D14 | Data Bus 14 |
60 | /DTACK | Data Transfer Acknowledge (normally asserted by Gary) |
61 | D13 | Data Bus 13 |
62 | R/W | Read/Write (high=read, low=write) |
63 | D12 | Data Bus 12 |
64 | /LDS | Lower Data Strobe |
65 | D11 | Data Bus 11 |
66 | /UDS | Upper Data Strobe |
67 | GND | Ground |
68 | /AS | Address Strobe |
69 | D0 | Data Bus 0 |
70 | D10 | Data Bus 10 |
71 | D1 | Data Bus 1 |
72 | D9 | Data Bus 9 |
73 | D2 | Data Bus 2 |
74 | D8 | Data Bus 8 |
75 | D3 | Data Bus 3 |
76 | D7 | Data Bus 7 |
77 | D4 | Data Bus 4 |
78 | D6 | Data Bus 6 |
79 | GND | Ground |
80 | D5 | Data Bus 5 |
Note: Pin 7-80 is equivalent with the Amiga 500's pin 13-86 at the 86 pin Amiga 500 connector.
Contributor: | Joakim Ögren |
Source: | Darren Ewaniuk's CDTV Technical Information |
Copyright © The Hardware Book Team 1996-2004.
May be copied and redistributed, partially or in whole, as appropriate.
Document last modified: 2002-01-10