McGraw-Hill ISBN 0-07-136172-3
List of Errata
page comment
vi Chapter 6: RIC should be R/C
61 Table 3-1 'Negationn' should be 'Negation'
76 Item 6 under 'Reset' is not correct/complete, see remarks for p.186
81 (1st sentence of "LOW_END DEVICES"
"The most obvious is the lack of addlw and sublw instructions,.."
but at that point these have not been mentioned in the book
(the index also doesn't have an earlier reference).
186 Table 5-4: WDT reset does NOT jump to the reset vector when in
sleep mode (see for example datasheet 30292B page 133/134)
External Interrupt: "Next/Instructions" -> "Next instruction"
(without 's', also with TMR1 Interrupt)
186 (after sleep nop code):
I don't understand "For _one_" etc. (which one?)
193 (middle): "... the bit itself is set for output." (-> input)
197 table 5-7: bit 6 PEIE - Device Specific
TOIE -> T0IE
TOIF -> T0IF
201 (middle of delay calculation)
160/1000000*4000000/8
204 table 5-10: TOCS -> T0CS
TOSE -> T0SE
PSO -> PS0
205 table 5-11: in header: Option -> OPTION (like in table 5-10)
_RBPU -> NOT_RBPU or RBPU_
TOCS - TMRO -> T0CS - TMR0
TOSE -> T0SE
206 (middle) "EECON and EECON2 are used to ..." -> "EECON1 ...
207 1st piece of code, line 6: "EECON1, ^ 0x08, RD" -> "EECON1 ^ ..."
2nd piece of code, line 6: "EECON 1 ^ 0x0180, RD" -> "EECON1 ..."
At least a reference to datasheets or so should be given.
(second section) "TMR1 ... has _four_ possible inputs". Which four?
(middle) "INTCON PIE bit" INTCON doesn't have a PIE bit,
should be "PEIE bit".
213 table 5-13 header: TICON -> T1CON
T1CPS1:T1CPS0 -> T1CKPS:T1CKPS0
T10SLEN -> T1OSCEN
(last section) 24-bit instruction cycle delay -> 18 bit
214 figure 5-30 TOUTPS2: -> TOUTPS3:
TMR1F -> TMR2F
(middle) "not synchronised" -> "not explicitly synchronised"
"can be incremented" -> "can only be incremented"
(bottom) Delay = (prescaler * [(PR2 + 1) | 256]) / ((Fosc/4)*postscaler)
215 table 5-14: 6-5 -> 6-3
2: omit the word 'Prescaler'
just below table: "... corresponding bits in TMR1" -> "... T1CON"
bottom line: CCPxMS: -> CCPXM3:
217 second line below fig 5-32: CCPRxM -> CCPRxH
219 top line: TMR1 -> TMR2
'its most-significant 8 bits are' -> 'it is'
3rd section: CCPRxM -> CCPRxH
formula is wrong: see correct formula on page 214
PR2 = delay * (freq/4) * 4 - 1
50 / 1000000 * 4000000 / 4 * 4 - 1
3rd line of code: "(1 << TMR2 on) + 11" -> "(1 << TMR2ON) + 0x01"
1-but-last line of code: text below says you don't use the
fractional bits, but the code sets DCxB1 (without space!)
220 3rd line: "DCxBX" -> "DCxBx"
230 USART chapter
... USART (Universal Synchronous Asynchronous Receiver Transmitter)
231 BRGH and SPBRG register not in index of the book
calculation of SPBRG, 2nd and 3rd line: missing "*" between 16 and [4
234 table 5-22: missing word "transmit" after description of bit 6
bit 0: "Nine" -> "Ninth"
235 bottom section: TRMT ... "TX holding register" -> "TX shift register"
bottom line: "saving" -> "storing"
278 Potmeter of 10 Ohm in Fig 6-25 should (probably) be 10 KOhm
790 (middle): What means "A TMR0 does not enable TMR0"
791 (middle of code): "addlw, 0" -> "addlw 0"
(addlw is not in index of Pocket reference)
832 (approx 10th line of code): "clrf TRISB & 0x7F ; Set all ..." ->
"... all bits _except RB7_ ..."
833 (third alinea): don't understand calculation with "/32"
4 Mhz -> 250 nanoseconds period
32 * 250 nanoseconds -> 8 microseconds
(8th line from bottom): "16C62X devices (fig 5-112)" -> "16F84 ..."
836 (last alinea): should explain WHY the difference
845 (middle) "TMR2 and TMR3" -> "TMR1 and TMR2"
869 figure 15-137: PIC1C73B -> PIC16C73B
881 figure 15-144: PIC1F84 -> PIC16F84
952 figure 16-31: U2 - L239D -> U2 - L293D
1034 table 16-35: third column: 100 -> 160
Rob Hamerling.